This application relates to hardware systems useful in implementing electronic neural network concepts.
There has been a recent resurgence of interest in the neural network concept as a new approach to computing. "The collective behavior of neural network systems has demonstrated useful computational properties for associative memory functions, fault-tolerant pattern recognition, and combinatorial optimization problem solving." The preceding sentence is copied from "Electronic hardware implementations of neural networks" by Thakoor, Moopenn, Lambe, and Khanna, of the California Institute of Technology, published in Applied Optics, Vol. 26, page 5085, Dec. 1, 1987.
The quoted article also states: "The study of the dynamics, learning mechanisms, and computational properties of neural networks has been largely based on computer software simulations." Subsequently it discusses neural network hardware: "The availability of neural network hardware would greatly enhance the present efforts in neural network research. Furthermore, the hardware would not only serve as research tools to aid in the development and evaluation of neural network concepts, but they would also provide the basis for development of application-specific architectures for implementing neural network approaches to real-life problems".
The present application discloses a novel approach to solving the major problems involved in providing hardware implementation of electronic neural networks.
The article quoted above identifies (pages 5087-5088) several research programs directed toward developing electronic neural network hardware. The requirements of neural network hardware include extreme interconnection capabilities, i.e., each of many parallel signals must have access to all of the other signals via individual weighted feedback networks. Also the processing nodes which are responsible for decision making must have bi-directional selective access to innumerable incoming signals.
The assignee of this application has been a leader in developing three-dimensional readout arrays for imaging sensor systems. Neural networks offer the potential for a quantum leap in the capabilities of imaging sensor systems. The critical neural network implementation factors are: weighted interconnect between all detector outputs; parallel, linear processing of each detector output; fan-out to multiple (thousands of) processing nodes per detector output; and the ability to independently change interconnect weights and processor node connections within the detector integration times. For a 128.times.128 pixel detector array, the number of desirable interconnects could be as high as 10.sup.15 per second, compared to the approximate 10.sup.9 rates achieved presently with off-focal plane digital processors. This application describes a new way of interconnecting three-dimensional focal plane readout modules and of laying out their component integrated circuits that appears to fulfill the very high interconnect rate requirements of neural networks.